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MICRO
2010
IEEE
156views Hardware» more  MICRO 2010»
15 years 5 months ago
Explicit Communication and Synchronization in SARC
SARC merges cache controller and network interface functions by relying on a single hardware primitive: each access checks the tag and the state of the addressed line for possible...
Manolis Katevenis, Vassilis Papaefstathiou, Stamat...
RV
2010
Springer
177views Hardware» more  RV 2010»
15 years 5 months ago
Runtime Instrumentation for Precise Flow-Sensitive Type Analysis
We describe a combination of runtime information and static analysis for checking properties of complex and configurable systems. The basic idea of our approach is to 1) let the p...
Etienne Kneuss, Philippe Suter, Viktor Kuncak
WABI
2010
Springer
128views Bioinformatics» more  WABI 2010»
15 years 4 months ago
Sparsification of RNA Structure Prediction Including Pseudoknots
Background: Although many RNA molecules contain pseudoknots, computational prediction of pseudoknotted RNA structure is still in its infancy due to high running time and space con...
Mathias Möhl, Raheleh Salari, Sebastian Will,...
CASES
2010
ACM
15 years 4 months ago
Implementing virtual secure circuit using a custom-instruction approach
Although cryptographic algorithms are designed to resist at least thousands of years of cryptoanalysis, implementing them with either software or hardware usually leaks additional...
Zhimin Chen, Ambuj Sinha, Patrick Schaumont
CASES
2010
ACM
15 years 4 months ago
Balancing memory and performance through selective flushing of software code caches
Dynamic binary translators (DBTs) are becoming increasingly important because of their power and flexibility. However, the high memory demands of DBTs present an obstacle for all ...
Apala Guha, Kim M. Hazelwood, Mary Lou Soffa
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