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ISSS
1999
IEEE
151views Hardware» more  ISSS 1999»
15 years 11 months ago
Optimized System Synthesis of Complex RT Level Building Blocks from Multirate Dataflow Graphs
In order to cope with the ever increasing complexity of todays application specific integrated circuits, a building block based design methodology is established. The system is co...
Jens Horstmannshoff, Heinrich Meyr
IPPS
1997
IEEE
15 years 11 months ago
MTIO - A Multi-Threaded Parallel I/O System
This paper presents the design and evaluation of a multithreaded runtime library for parallel I/O. We extend the multi-threading concept to separate the compute and I/O tasks in t...
Sachin More, Alok N. Choudhary, Ian T. Foster, Min...
IMS
2000
123views Hardware» more  IMS 2000»
15 years 10 months ago
Exploiting On-Chip Memory Bandwidth in the VIRAM Compiler
Many architectural ideas that appear to be useful from a hardware standpoint fail to achieve wide acceptance due to lack of compiler support. In this paper we explore the design of...
David Judd, Katherine A. Yelick, Christoforos E. K...
DEXAW
2008
IEEE
126views Database» more  DEXAW 2008»
15 years 8 months ago
Incorporating Database Systems into a Secure Software Development Methodology
We have proposed in the past three separate methodologies for secure software development. We have found that they have many common and complementary aspects and we proposed a com...
Eduardo B. Fernández, Jan Jürjens, Nob...
ISLPED
2007
ACM
96views Hardware» more  ISLPED 2007»
15 years 8 months ago
Low-power process-variation tolerant arithmetic units using input-based elastic clocking
In this paper we propose a design methodology for low-power, high-performance, process-variation tolerant architecture for arithmetic units. The novelty of our approach lies in th...
Debabrata Mohapatra, Georgios Karakonstantis, Kaus...