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DSN
2011
IEEE
14 years 6 months ago
Transparent dynamic binding with fault-tolerant cache coherence protocol for chip multiprocessors
—Aggressive technology scaling causes chip multiprocessors increasingly error-prone. Core-level faulttolerant approaches bind two cores to implement redundant execution and error...
Shuchang Shan, Yu Hu, Xiaowei Li
IC
2003
15 years 7 months ago
Remote Real Laboratory: Linux Installation and Configuration
: Remote real laboratories deal with performing real lab experiments remotely via Internet. Recent advances in Internet/web technologies and computer-controlled instrumentation all...
Alassane Diop, Amine Berqia, Jürgen Harms
STOC
2012
ACM
225views Algorithms» more  STOC 2012»
13 years 8 months ago
An algorithmic characterization of multi-dimensional mechanisms
We obtain a characterization of feasible, Bayesian, multi-item multi-bidder mechanisms with independent, additive bidders as distributions over hierarchical mechanisms. Combined w...
Yang Cai, Constantinos Daskalakis, S. Matthew Wein...
VLDB
2005
ACM
152views Database» more  VLDB 2005»
16 years 6 months ago
Composing, optimizing, and executing plans for bioinformatics web services
The emergence of a large number of bioinformatics datasets on the Internet has resulted in the need for flexible and efficient approaches to integrate information from multiple bio...
Snehal Thakkar, José Luis Ambite, Craig A. Knoblo...
ICCAD
1999
IEEE
115views Hardware» more  ICCAD 1999»
15 years 10 months ago
Fast performance analysis of bus-based system-on-chip communication architectures
This paper addresses the problem of efficient and accurate performance analysis to drive the exploration and design of bus-based System-on-Chip (SOC) communication architectures. ...
Kanishka Lahiri, Anand Raghunathan, Sujit Dey