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» Trusted Design in FPGAs
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DAC
2000
ACM
16 years 7 months ago
Depth optimal incremental mapping for field programmable gate arrays
In this paper, we study the incremental t echnology mapping problem for lookup-table (LUT) based Field Programmable Gate Arrays (FPGAs) under incremental changes. Given a gate-lev...
Jason Cong, Hui Huang
CHES
2009
Springer
171views Cryptology» more  CHES 2009»
16 years 7 months ago
Trojan Side-Channels: Lightweight Hardware Trojans through Side-Channel Engineering
Abstract. The general trend in semiconductor industry to separate design from fabrication leads to potential threats from untrusted integrated circuit foundries. In particular, mal...
Christof Paar, Lang Lin, Markus Kasper, Tim Gü...
FPGA
2010
ACM
243views FPGA» more  FPGA 2010»
16 years 3 months ago
Bit-level optimization for high-level synthesis and FPGA-based acceleration
d hardware design from behavior-level abstraction has drawn wide interest in FPGA-based acceleration and configurable computing research field. However, for many high-level progra...
Jiyu Zhang, Zhiru Zhang, Sheng Zhou, Mingxing Tan,...
AHS
2007
IEEE
252views Hardware» more  AHS 2007»
16 years 26 days ago
A Hybrid Engine for the Placement of Domain-Specific Reconfigurable Arrays
Rapid-prototyping of commercial devices and the demanding requirements for flexible hardware in mobile applications have driven the raise of reconfigurable hardware. The adaptatio...
Wing On Fung, Tughrul Arslan, Sami Khawam
FCCM
2007
IEEE
100views VLSI» more  FCCM 2007»
16 years 22 days ago
A Library and Platform for FPGA Bitstream Manipulation
— Since 1998, no commercially available FPGA has been accompanied by public documentation of its native machine code (or bitstream) format. Consequently, research in reconfigura...
Adam Megacz