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FDTC
2008
Springer
87views Cryptology» more  FDTC 2008»
15 years 8 months ago
Silicon-level Solutions to Counteract Passive and Active Attacks
This article presents a family of cryptographic ASICs, called SecMat, designed in CMOS 130 nanometer technology by the authors with the help of STMicroelectronics. The purpose of ...
Sylvain Guilley, Laurent Sauvage, Jean-Luc Danger,...
ERSA
2008
145views Hardware» more  ERSA 2008»
15 years 8 months ago
Multicore Devices: A New Generation of Reconfigurable Architectures
For two decades, reconfigurable computing systems have provided an attractive alternative to fixed hardware solutions. Reconfigurable computing systems have demonstrated the low c...
Steven A. Guccione
ERSA
2006
99views Hardware» more  ERSA 2006»
15 years 8 months ago
Low Power Programmable FIR Filtering IP Cores Targeting System-on-a-Reprogrammable-Chip (SoRC)
- This paper presents the design and implementation methodology of some low power programmable FIR filtering IP cores targeting SoRC and compares their performance in term of area,...
Muhammad Akhtar Khan, Abdul Hameed, Ahmet T. Erdog...
WCE
2007
15 years 7 months ago
High-Performance Multigrid Solvers in Reconfigurable Hardware
—Partial Differential Equations (PDEs) play an essential role in modeling real world problems. The broad field of modeling such systems has drawn the researchers’ attention for...
Safaa J. Kasbah, Issam W. Damaj
VLSISP
2011
216views Database» more  VLSISP 2011»
15 years 1 months ago
Accurate Area, Time and Power Models for FPGA-Based Implementations
This paper presents accurate area, time, power estimation models for implementations using FPGAs from the Xilinx Virtex-2Pro family [1]. These models are designed to facilitate ef...
Lanping Deng, Kanwaldeep Sobti, Yuanrui Zhang, Cha...