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CAV
1998
Springer
175views Hardware» more  CAV 1998»
15 years 11 months ago
An ACL2 Proof of Write Invalidate Cache Coherence
As a pedagogical exercise in ACL2, we formalize and prove the correctness of a write invalidate cache scheme. In our formalization, an arbitrary number of processors, each with its...
J. Strother Moore
QCQC
1998
Springer
173views Communications» more  QCQC 1998»
15 years 11 months ago
Quantum Wavelet Transforms: Fast Algorithms and Complete Circuits
The quantum Fourier transform (QFT), a quantum analog of the classical Fourier transform, has been shown to be a powerful tool in developing quantum algorithms. However, in classi...
Amir Fijany, Colin P. Williams
PLDI
1997
ACM
15 years 11 months ago
Flick: A Flexible, Optimizing IDL Compiler
An interface definition language (IDL) is a nontraditional language for describing interfaces between software components. IDL compilers generate “stubs” that provide separat...
Eric Eide, Kevin Frei, Bryan Ford, Jay Lepreau, Ga...
ISCA
1996
IEEE
130views Hardware» more  ISCA 1996»
15 years 11 months ago
Informing Memory Operations: Providing Memory Performance Feedback in Modern Processors
Memory latency is an important bottleneck in system performance that cannot be adequately solved by hardware alone. Several promising software techniques have been shown to addres...
Mark Horowitz, Margaret Martonosi, Todd C. Mowry, ...
ASPDAC
2007
ACM
121views Hardware» more  ASPDAC 2007»
15 years 11 months ago
Ultralow-Power Reconfigurable Computing with Complementary Nano-Electromechanical Carbon Nanotube Switches
In recent years, several alternative devices have been proposed to deal with inherent limitation of conventional CMOS devices in terms of scalability at nanometer scale geometry. ...
Swarup Bhunia, Massood Tabib-Azar, Daniel G. Saab