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ASPLOS
1998
ACM
15 years 11 months ago
Space-Time Scheduling of Instruction-Level Parallelism on a Raw Machine
Advances in VLSI technology will enable chips with over a billion transistors within the next decade. Unfortunately, the centralized-resource architectures of modern microprocesso...
Walter Lee, Rajeev Barua, Matthew Frank, Devabhakt...
ASPLOS
1992
ACM
15 years 10 months ago
High Speed Switch Scheduling for Local Area Networks
Current technology trends make it possible to build communication networks that can support high performance distributed computing. This paper describes issues in the design of a ...
Thomas E. Anderson, Susan S. Owicki, James B. Saxe...
ICCD
2007
IEEE
195views Hardware» more  ICCD 2007»
15 years 10 months ago
LEMap: Controlling leakage in large chip-multiprocessor caches via profile-guided virtual address translation
The emerging trend of larger number of cores or processors on a single chip in the server, desktop, and mobile notebook platforms necessarily demands larger amount of on-chip last...
Jugash Chandarlapati, Mainak Chaudhuri
CCGRID
2004
IEEE
15 years 10 months ago
DWDM-RAM: a data intensive Grid service architecture enabled by dynamic optical networks
Next generation applications and architectures (for example, Grids) are driving radical changes in the nature of traffic, service models, technology, and cost, creating opportunit...
Tal Lavian, Joe Mambretti, Doug Cutrell, Howard J....
DATE
2004
IEEE
185views Hardware» more  DATE 2004»
15 years 10 months ago
Energy-Aware System Design for Wireless Multimedia
In this paper, we present various challenges that arise in the delivery and exchange of multimedia information to mobile devices. Specifically, we focus on techniques for maintain...
Hans Van Antwerpen, Nikil D. Dutt, Rajesh K. Gupta...