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DAC
2004
ACM
16 years 7 months ago
A method for correcting the functionality of a wire-pipelined circuit
As across-chip interconnect delays can exceed a clock cycle, wire pipelining becomes essential in high performance designs. Although it allows higher clock frequencies, it may cha...
Vidyasagar Nookala, Sachin S. Sapatnekar
DAC
2005
ACM
16 years 7 months ago
Race-condition-aware clock skew scheduling
The race conditions often limit the smallest feasible clock period that the optimal clock skew scheduling can achieve. Therefore, the combination of clock skew scheduling and dela...
Shih-Hsu Huang, Yow-Tyng Nieh, Feng-Pin Lu
ICML
2009
IEEE
16 years 7 months ago
Multi-assignment clustering for Boolean data
Conventional clustering methods typically assume that each data item belongs to a single cluster. This assumption does not hold in general. In order to overcome this limitation, w...
Andreas P. Streich, Mario Frank, David A. Basin, J...
ICML
2009
IEEE
16 years 7 months ago
Prototype vector machine for large scale semi-supervised learning
Practical data mining rarely falls exactly into the supervised learning scenario. Rather, the growing amount of unlabeled data poses a big challenge to large-scale semi-supervised...
Kai Zhang, James T. Kwok, Bahram Parvin
ICML
2005
IEEE
16 years 7 months ago
Linear Asymmetric Classifier for cascade detectors
The detection of faces in images is fundamentally a rare event detection problem. Cascade classifiers provide an efficient computational solution, by leveraging the asymmetry in t...
Jianxin Wu, Matthew D. Mullin, James M. Rehg