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ICPP
1997
IEEE
15 years 11 months ago
How Much Does Network Contention Affect Distributed Shared Memory Performance?
Most of recent research on distributed shared memory (DSM)systems have focused on either careful design of node controllersor cache coherenceprotocols. Whileevaluating these desig...
Donglai Dai, Dhabaleswar K. Panda
ANCS
2009
ACM
15 years 4 months ago
Design and performance analysis of a DRAM-based statistics counter array architecture
The problem of maintaining efficiently a large number (say millions) of statistics counters that need to be updated at very high speeds (e.g. 40 Gb/s) has received considerable re...
Haiquan (Chuck) Zhao, Hao Wang, Bill Lin, Jun (Jim...
DAC
2012
ACM
13 years 9 months ago
Cache revive: architecting volatile STT-RAM caches for enhanced performance in CMPs
Spin-Transfer Torque RAM (STT-RAM) is an emerging non-volatile memory (NVM) technology that has the potential to replace the conventional on-chip SRAM caches for designing a more ...
Adwait Jog, Asit K. Mishra, Cong Xu, Yuan Xie, Vij...
HPCC
2007
Springer
15 years 10 months ago
An Exploration of Performance Attributes for Symbolic Modeling of Emerging Processing Devices
Vector, emerging (homogenous and heterogeneous) multi-core and a number of accelerator processing devices potentially offer an order of magnitude speedup for scientific application...
Sadaf R. Alam, Nikhil Bhatia, Jeffrey S. Vetter
SC
2005
ACM
16 years 6 days ago
Cross-Platform Performance Prediction of Parallel Applications Using Partial Execution
Performance prediction across platforms is increasingly important as developers can choose from a wide range of execution platforms. The main challenge remains to perform accurate...
Leo T. Yang, Xiaosong Ma, Frank Mueller