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HIPC
2004
Springer
16 years 7 hour ago
Parallel Performance of Hierarchical Multipole Algorithms for Inductance Extraction
Parasitic extraction techniques are used to estimate signal delay in VLSI chips. Inductance extraction is a critical component of the parasitic extraction process in which on-chip ...
Hemant Mahawar, Vivek Sarin, Ananth Grama
AINA
2009
IEEE
15 years 11 months ago
An Analytical Performance Evaluation for WSNs Using Loop-Free Bellman Ford Protocol
—Although several analytical models have been proposed for wireless sensor networks (WSNs) with different capabilities, very few of them consider the effect of general service di...
Mohammad Baharloo, Reza Hajisheykhi, Mohammad Arjo...
IEEEPACT
2002
IEEE
15 years 11 months ago
Optimizing Loop Performance for Clustered VLIW Architectures
Modern embedded systems often require high degrees of instruction-level parallelism (ILP) within strict constraints on power consumption and chip cost. Unfortunately, a high-perfo...
Yi Qian, Steve Carr, Philip H. Sweany
PERCOM
2010
ACM
15 years 10 months ago
Negotiate power and performance in the reality of RFID systems
—Recent years have witnessed the wide adoption of the RFID technology in many important application domains including logistics, inventory, retailing, public transportation, and ...
Xunteng Xu, Lin Gu, Jianping Wang, Guoliang Xing
DAC
1999
ACM
16 years 7 months ago
Simultaneous Circuit Partitioning/Clustering with Retiming for Performance Optimization
Partitioning and clustering are crucial steps in circuit layout for handling large scale designs enabled by the deep submicron technologies. Retiming is an important sequential lo...
Jason Cong, Honching Li, Chang Wu