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ISLPED
2004
ACM
137views Hardware» more  ISLPED 2004»
15 years 12 months ago
Location cache: a low-power L2 cache system
While set-associative caches incur fewer misses than directmapped caches, they typically have slower hit times and higher power consumption, when multiple tag and data banks are p...
Rui Min, Wen-Ben Jone, Yiming Hu
ISSTA
2004
ACM
15 years 12 months ago
Verifying process models built using parameterized state machines
Software process and workflow languages are increasingly used to define loosely-coupled systems of systems. These languages focus on coordination issues such as data flow and c...
Barbara Staudt Lerner
ICS
2004
Tsinghua U.
15 years 11 months ago
Evaluating support for global address space languages on the Cray X1
The Cray X1 was recently introduced as the first in a new line of parallel systems to combine high-bandwidth vector processing with an MPP system architecture. Alongside capabili...
Christian Bell, Wei-Yu Chen, Dan Bonachea, Katheri...
CLUSTER
2003
IEEE
15 years 11 months ago
A Performance Monitor Based on Virtual Global Time for Clusters of PCs
Debugging the performance of parallel and distributed systems remains a difficult task despite the widespread use of middleware packages for automatic distribution, communication...
Michela Taufer, Thomas Stricker
MICRO
2003
IEEE
125views Hardware» more  MICRO 2003»
15 years 11 months ago
WaveScalar
Silicon technology will continue to provide an exponential increase in the availability of raw transistors. Effectively translating this resource into application performance, how...
Steven Swanson, Ken Michelson, Andrew Schwerin, Ma...
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