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CODES
2005
IEEE
16 years 2 days ago
High-level synthesis for large bit-width multipliers on FPGAs: a case study
In this paper, we present the analysis, design and implementation of an estimator to realize large bit width unsigned integer multiplier units. Larger multiplier units are require...
Gang Quan, James P. Davis, Siddhaveerasharan Devar...
ICAC
2007
IEEE
16 years 24 days ago
SLA Decomposition: Translating Service Level Objectives to System Level Thresholds
In today’s complex and highly dynamic computing environments, systems/services have to be constantly adjusted to meet Service Level Agreements (SLAs) and to improve resource uti...
Yuan Chen, Subu Iyer, Xue Liu, Dejan S. Milojicic,...
IPPS
2002
IEEE
15 years 11 months ago
Variable Partitioning and Scheduling of Multiple Memory Architectures for DSP
Multiple memory module architecture enjoys higher memory access bandwidth and thus higher performance. Two key problems in gaining high performance in this kind of architecture ar...
Qingfeng Zhuge, Bin Xiao, Edwin Hsing-Mean Sha
IPPS
2009
IEEE
16 years 1 months ago
A component-based framework for the Cell Broadband Engine
With the increasing trend of microprocessor manufacturers to rely on parallelism to increase their products’ performance, there is an associated increasing need for simple techn...
Timothy D. R. Hartley, Ümit V. Çataly&...
CIVR
2007
Springer
104views Image Analysis» more  CIVR 2007»
16 years 19 days ago
Semantic facets: an in-depth analysis of a semantic image retrieval system
This paper introduces a faceted model of image semantics which attempts to express the richness of semantic content interpretable within an image. Using a large image data-set fro...
Jonathon S. Hare, Paul H. Lewis, Peter G. B. Enser...