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IPPS
2007
IEEE
16 years 22 days ago
A Study of Design Efficiency with a High-Level Language for FPGAs
Over the years reconfigurable computing devices such as FPGAs have evolved from gate-level glue logic to complex reprogrammable processing architectures. However, the tools used f...
Zain-ul-Abdin, Bertil Svensson
ISPA
2007
Springer
16 years 17 days ago
Parallelization Strategies for the Points of Interests Algorithm on the Cell Processor
The Cell processor is a typical example of a heterogeneous multiprocessor-on-chip architecture that uses several levels of parallelism to deliver high performance. Closing the gap ...
Tarik Saidani, Lionel Lacassagne, Samir Bouaziz, T...
ICIP
2006
IEEE
16 years 14 days ago
Extracting Static Hand Gestures in Dynamic Context
Cued Speech is a specific visual coding that complements oral language lip-reading, by adding static hand gestures (a static gesture can be presented on a single photograph as it ...
Thomas Burger, Alexandre Benoit, Alice Caplier
SRDS
1997
IEEE
15 years 10 months ago
Fault Detection Using Hints from the Socket Layer
This paper describes a fault detection mechanism that uses the error codes returned by the stream sockets to locate process failures. Since these errors are generated automaticall...
Nuno Neves, W. Kent Fuchs
CORR
2010
Springer
124views Education» more  CORR 2010»
15 years 6 months ago
Detecting Danger: The Dendritic Cell Algorithm
l invaders in the form of pathogens. In this research, and abstract model of DC behaviour is developed and subsequently used to form an algorithm, the DCA. The abstraction process ...
Julie Greensmith, Uwe Aickelin, Steve Cayzer