145 search results - page 4 / 29 » Towards an efficient switch architecture for high-radix swit... |
138
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DAC
2005
ACM
2005
ACM
Leakage efficient chip-level dual-Vdd assignment with time slack allocation for FPGA power reduction
16 years 7 months ago
To reduce power, Vdd programmability has been proposed recently to select Vdd-level for interconnects and to powergate unused interconnects. However, Vdd-level converters used in ...
148
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ICC
2000
IEEE
15 years 10 months ago
2000
IEEE
— We consider cell-based switch architectures in which the speedup of the internal switching fabric is not large enough to avoid input buffering. These architectures require a sc...
201
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ISCA
2006
IEEE
15 years 6 months ago
2006
IEEE
Packet-based on-chip networks are increasingly being adopted in complex System-on-Chip (SoC) designs supporting numerous homogeneous and heterogeneous functional blocks. These Net...
163
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HIPEAC
2005
Springer
15 years 11 months ago
2005
Springer
Abstract. Designers of large parallel computers and clusters are becoming increasingly concerned with the cost and power consumption of the interconnection network. A simple way to...
186
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INFOCOM
1999
IEEE
15 years 10 months ago
1999
IEEE
With the proliferation of high-speed networks and networked services, provisioning differentiated services to a diverse user base with heterogeneous QoS requirements has become an ...