A physical yet compact gate delay model is developed integrating short-channel effects and the Alpha-power law based timing model. This analytical approach accurately predicts bot...
In this paper, we present a unified approach to evaluating the relative expressive power of process calculi. In particular, we identify a small set of criteria (that have already b...
Modern commodity hardware architectures, with their multiple multi-core CPUs and high-speed system interconnects, exhibit tremendous power. In this paper, we study performance lim...
Norbert Egi, Adam Greenhalgh, Mark Handley, Micka&...
Enterprise networks are important, with size and complexity even surpassing carrier networks. Yet, the design of enterprise networks remains ad-hoc and poorly understood. In this p...
Yu-Wei Eric Sung, Sanjay G. Rao, Geoffrey G. Xie, ...
In response to the limitations of the Internet architecture when used for applications for which it was not originally designed, a series of clean slate efforts have emerged to sh...