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IPPS
2007
IEEE
16 years 18 days ago
Towards Optimal Multi-level Tiling for Stencil Computations
Stencil computations form the performance-critical core of many applications. Tiling and parallelization are two important optimizations to speed up stencil computations. Many til...
Lakshminarayanan Renganarayanan, Manjukumar Harthi...
ASAP
2007
IEEE
175views Hardware» more  ASAP 2007»
15 years 8 months ago
Scalable Multi-FPGA Platform for Networks-On-Chip Emulation
Interconnect validation is an important early step toward global SoC (System-On-Chip) validation. Fast performances evaluation and design space exploration for NoCs (Networks-On-C...
Abdellah-Medjadji Kouadri-Mostefaoui, Benaoumeur S...
CGF
2010
121views more  CGF 2010»
15 years 6 months ago
GraphDice: A System for Exploring Multivariate Social Networks
Social networks collected by historians or sociologists typically have a large number of actors and edge attributes. Applying social network analysis (SNA) algorithms to these net...
Anastasia Bezerianos, Fanny Chevalier, Pierre Drag...
HPDC
2009
IEEE
16 years 1 months ago
Exploring data reliability tradeoffs in replicated storage systems
This paper explores the feasibility of a cost-efficient storage architecture that offers the reliability and access performance characteristics of a high-end system. This architec...
Abdullah Gharaibeh, Matei Ripeanu
CODES
2006
IEEE
16 years 10 days ago
A formal approach to robustness maximization of complex heterogeneous embedded systems
Embedded system optimization typically considers objectives such as cost, timing, buffer sizes and power consumption. Robustness criteria, i.e. sensitivity of the system to variat...
Arne Hamann, Razvan Racu, Rolf Ernst