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» Topology generation based on network design heuristics
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ISLPED
2010
ACM
181views Hardware» more  ISLPED 2010»
15 years 4 months ago
Exploiting power budgeting in thermal-aware dynamic placement for reconfigurable systems
 In this paper, a novel thermal-aware dynamic placement planner for reconfigurable systems is presented, which targets transient temperature reduction. Rather than solving time-...
Shahin Golshan, Eli Bozorgzadeh, Benjamin Carri&oa...
ICC
2007
IEEE
121views Communications» more  ICC 2007»
16 years 18 days ago
Scalable Resilient Overlay Networks Using Destination-Guided Detouring
— Routing policies used in the Internet tend to be restrictive limiting communication between source-destination pairs to one route, when often better alternates exist. To avoid ...
Sameer Qazi, Tim Moors
DATE
2003
IEEE
103views Hardware» more  DATE 2003»
15 years 11 months ago
Reduced Delay Uncertainty in High Performance Clock Distribution Networks
The design of clock distribution networks in synchronous digital systems presents enormous challenges. Controlling the clock signal delay in the presence of various noise sources,...
Dimitrios Velenis, Marios C. Papaefthymiou, Eby G....
DAC
1999
ACM
15 years 10 months ago
Behavioral Synthesis of Analog Systems Using Two-layered Design Space Exploration
This paper presents a novel approach for synthesis of analog systems from behavioral VHDL-AMS specifications. We implemented this approach in the VASE behavioral-synthesis tool. ...
Alex Doboli, Adrián Núñez-Ald...
ASPDAC
2006
ACM
143views Hardware» more  ASPDAC 2006»
16 years 8 days ago
CDCTree: novel obstacle-avoiding routing tree construction based on current driven circuit model
Abstract— Routing tree construction is a fundamental problem in modern VLSI design. In this paper we propose CDCTree, an Obstacle-Avoiding Rectilinear Steiner Minimum Tree (OARSM...
Yiyu Shi, Tong Jing, Lei He, Zhe Feng 0002, Xianlo...