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» Topology generation based on network design heuristics
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IWMM
1992
Springer
100views Hardware» more  IWMM 1992»
15 years 10 months ago
Scalable Distributed Garbage Collection for Systems of Active Objects
Abstract. Automatic storage management is important in highly parallel programming environments where large numbers of objects and processes are being constantly created and discar...
Nalini Venkatasubramanian, Gul Agha, Carolyn L. Ta...
ICMLA
2010
15 years 4 months ago
Nonlinear Dynamical Multi-Scale Model of Associative Memory
How can we get such reliable behavior from the mind when the brain is made up of such unreliable elements as neurons? We propose that the answer is related to the emergence of stab...
Alexander M. Duda, Stephen E. Levinson
MSWIM
2005
ACM
15 years 12 months ago
Latency-sensitive power control for wireless ad-hoc networks
We investigate the impact of power control on latency in wireless ad-hoc networks. If transmission power is increased, interference increases, thus reducing network capacity. A no...
Mohamed R. Fouad, Sonia Fahmy, Gopal Pandurangan
TCAD
2008
128views more  TCAD 2008»
15 years 6 months ago
Obstacle-Avoiding Rectilinear Steiner Tree Construction Based on Spanning Graphs
Given a set of pins and a set of obstacles on a plane, an obstacle-avoiding rectilinear Steiner minimal tree (OARSMT) connects these pins, possibly through some additional points (...
Chung-Wei Lin, Szu-Yu Chen, Chi-Feng Li, Yao-Wen C...
SDL
2003
147views Hardware» more  SDL 2003»
15 years 7 months ago
Modelling and Evaluation of a Network on Chip Architecture Using SDL
Network on Chip (NoC) is a new paradigm for designing large and complex systems on chips (SoCs). In this paradigm, a packet switched network is provided for on-chip communication. ...
Rickard Holsmark, Magnus Högberg, Shashi Kuma...