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IAJIT
2010
150views more  IAJIT 2010»
15 years 5 months ago
Optimal DSP Based Integer Motion Estimation Implementation for H.264/AVC Baseline Encoder
: The coding gain of the H.264/AVC video encoder mainly comes from the new incorporated prediction tools. However, their enormous computation and ultrahigh memory bandwidth are the...
Imen Werda, Haithem Chaouch, Amine Samet, Mohamed ...
IPSN
2005
Springer
16 years 6 days ago
Lossy network correlated data gathering with high-resolution coding
— We consider a sensor network measuring correlated data, where the task is to gather all data from the network nodes to a sink. We consider the case where data at nodes is lossy...
Razvan Cristescu, Baltasar Beferull-Lozano
ICCAD
1997
IEEE
142views Hardware» more  ICCAD 1997»
15 years 11 months ago
Library-less synthesis for static CMOS combinational logic circuits
Traditional synthesis techniques optimize CMOS circuits in two phases i) logic minimization and ii) library mapping phase. Typically, the structures and the sizes of the gates in ...
Sergey Gavrilov, Alexey Glebov, Satyamurthy Pullel...
ICCAD
2006
IEEE
96views Hardware» more  ICCAD 2006»
16 years 3 months ago
Loop pipelining for high-throughput stream computation using self-timed rings
We present a technique for increasing the throughput of stream processing architectures by removing the bottlenecks caused by loop structures. We implement loops as self-timed pip...
Gennette Gill, John Hansen, Montek Singh
FCCM
2005
IEEE
124views VLSI» more  FCCM 2005»
16 years 9 days ago
Parallel Hardware Implementation of Cellular Learning Automata Based Evolutionary Computing (CLA-EC) on FPGA
The CLA-EC is a model obtained by combining the concepts of cellular learning automata and evolutionary algorithms. The parallel structure of the CLA-EC makes it suitable for hard...
Arash Hariri, Reza Rastegar, Morteza Saheb Zamani,...