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DDECS
2007
IEEE
105views Hardware» more  DDECS 2007»
16 years 1 months ago
Layout to Logic Defect Analysis for Hierarchical Test Generation
- As shown by previous studies, shorts between the interconnect wires should be considered as the predominant cause of failures in CMOS circuits. Fault models and tools for targeti...
Maksim Jenihhin, Jaan Raik, Raimund Ubar, Witold A...
ECBS
2007
IEEE
144views Hardware» more  ECBS 2007»
16 years 1 months ago
DP-Miner: Design Pattern Discovery Using Matrix
Design patterns document expert design experience in software system development. They have been applied in many existing software systems. However, pattern information is general...
Jing Dong, Dushyant S. Lad, Yajing Zhao
EDOC
2007
IEEE
16 years 1 months ago
Survey of Traceability Approaches in Model-Driven Engineering
Models have been used in various engineering fields to help managing complexity and represent information in difbstraction levels, according to specific notations and stakeholde...
Ismênia Galvão, Arda Goknil
ESCIENCE
2007
IEEE
16 years 1 months ago
Towards a Grid-Enabled Simulation Framework for Nano-CMOS Electronics
The electronics design industry is facing major challenges as transistors continue to decrease in size. The next generation of devices will be so small that the position of indivi...
Liangxiu Han, Asen Asenov, Dave Berry, Campbell Mi...
FBIT
2007
IEEE
16 years 1 months ago
Evaluation of a Dominance-Based Rough Set Approach to Interface Design
This paper explores refinements to methods used in a procedure being developed by the authors to personalize user interfaces for online shopping support tools. In the authors’ ...
Timothy Maciag, Daryl H. Hepting, Robert J. Hilder...