4164 search results - page 96 / 833 » Timing model reduction for hierarchical timing analysis |
165
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ASPDAC
2006
ACM
16 years 8 days ago
2006
ACM
As technology scales down, timing verification of digital integrated circuits becomes an increasingly challenging task due to the gate and wire variability. Therefore, statistical...
154
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DATE
2003
IEEE
15 years 11 months ago
2003
IEEE
The growing impact of within-die process variation has created the need for statistical timing analysis, where gate delays are modeled as random variables. Statistical timing anal...
189
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ISPD
2005
ACM
15 years 12 months ago
2005
ACM
The sustained progress of VLSI technology has altered the landscape of routing which is a major physical design stage. For timing driven routings, traditional approaches which con...
208
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TOSEM
2010
15 years 1 months ago
2010
Web services are increasingly gaining acceptance as a framework for facilitating application-to-application interactions within and across enterprises. It is commonly accepted tha...
147
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DATE
2006
IEEE
16 years 11 days ago
2006
IEEE
This paper focuses on statistical interconnect timing analysis in a parameterized block-based statistical static timing analysis tool. In particular, a new framework for performin...