4164 search results - page 90 / 833 » Timing model reduction for hierarchical timing analysis |
134
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ICCAD
2006
IEEE
16 years 3 months ago
2006
IEEE
— Trajectory-based methods offer an attractive methodology for automated, on-demand generation of macromodels for custom circuits. These models are generated by sampling the stat...
153
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RTCSA
1999
IEEE
15 years 10 months ago
1999
IEEE
In this paper we present a technique for Worst-Case Execution Time WCET analysis for pipelined processors. Our technique uses a standard simulator instead of special-purpose pipel...
179
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DAC
1996
ACM
15 years 10 months ago
1996
ACM
-- This paper presents an efficient method for the timing verification of concurrent systems, modeled as labeled Timed Petri nets. The verification problems we consider require us ...
160
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ISQED
2009
IEEE
16 years 1 months ago
2009
IEEE
A system-level statistical analysis methodology is described that captures the impact of inter- and intra-die process variations for read timing failures in SRAM circuit blocks. U...
136
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DATE
2006
IEEE
16 years 11 days ago
2006
IEEE
State of the art statistical timing analysis (STA) tools often yield less accurate results when timing variables become correlated. Spatial correlation and correlation caused by p...