4164 search results - page 81 / 833 » Timing model reduction for hierarchical timing analysis |
168
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ICCAD
1999
IEEE
15 years 10 months ago
1999
IEEE
This paper presents a new method to synthesize timed asynchronous circuits directly from the specification without generating a state graph. The synthesis procedure begins with a ...
176
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TASE
2007
IEEE
16 years 16 days ago
2007
IEEE
Software has been under scrutiny by the verification community from various angles in the recent past. There are two major algorithmic approaches to ensure the correctness of and...
167
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ICCAD
2003
IEEE
15 years 11 months ago
2003
IEEE
Process variations have become a critical issue in performance verification of high-performance designs. We present a new, statistical timing analysis method that accounts for int...
157
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MASCOTS
2007
15 years 7 months ago
2007
—To overcome the drawbacks of the Mobile IPv6 protocol on handling local mobility management, IETF proposed the HMIPv6 protocol which introduces an intermediate mobility anchor p...
179
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ISSS
2002
IEEE
15 years 11 months ago
2002
IEEE
Static timing analysis of embedded software is important for systems with hard real-time constraints. To accurately estimate time bounds, it is essential to model the underlying m...