4164 search results - page 714 / 833 » Timing model reduction for hierarchical timing analysis |
183
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JGAA
2006
15 years 6 months ago
2006
Visualization of circuits is an important research area in electronic design automation. One commonly accepted method to visualize a circuit aligns the gates to layers and uses or...
147
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PAMI
2008
15 years 6 months ago
2008
This paper addresses the problem of visual tracking under very general conditions: a possibly nonrigid target whose appearance may drastically change over time, general camera moti...
177
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TVLSI
2008
15 years 6 months ago
2008
Abstract--Technology scaling in the nanometer era has increased the transistor's susceptibility to process variations. The effects of such variations are having a huge impact ...
174
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TC
1998
15 years 6 months ago
1998
—High instruction cache hit rates are key to high performance. One known technique to improve the hit rate of caches is to minimize cache interference by improving the layout of ...
192
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PC
2010
15 years 4 months ago
2010
Compute unified device architecture (CUDA) is a software development platform that allows us to run C-like programs on the nVIDIA graphics processing unit (GPU). This paper prese...