4164 search results - page 653 / 833 » Timing model reduction for hierarchical timing analysis |
155
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ASPDAC
2006
ACM
16 years 15 days ago
2006
ACM
— Process variations in digital circuits make sequential circuit timing validation an extremely challenging task. In this paper, a Statistical Bellman-Ford (SBF) algorithm is pro...
194
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ICDE
2005
IEEE
16 years 4 days ago
2005
IEEE
Many location-based applications require constant monitoring of k-nearest neighbor (k-NN) queries over moving objects within a geographic area. Existing approaches to this problem...
163
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DATE
2002
IEEE
15 years 11 months ago
2002
IEEE
Advancing technology drives design technology and thus design automation EDA . How to model interconnect, how to handle degradation of signal integrity and increasing power densi...
157
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EUROPAR
2000
Springer
15 years 10 months ago
2000
Springer
This paper describes a toolset, PACE, that provides detailed predictive performance information throughout the implementation and execution stages of an application. It is structur...
177
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ACMSE
2008
ACM
15 years 8 months ago
2008
ACM
Indirection exists between the virtual objects that form the computer interface and the input devices through which the user interacts to manipulate these objects. This paper stud...