4164 search results - page 651 / 833 » Timing model reduction for hierarchical timing analysis |
163
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ELECTRONICMARKETS
2010
15 years 3 months ago
2010
We argue that certain theoretical commitments that underpin much existing Interorganisational Information Systems (IOIS) research at small scales become untenable when IOIS are st...
159
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VLSID
2002
IEEE
16 years 7 months ago
2002
IEEE
We present a mathematical model for the problem of scheduling tests for core-based system-on-chip (SOC) VLSI designs. Given a set of tests for each core in the SOC and a set of te...
168
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STOC
2005
ACM
16 years 6 months ago
2005
ACM
We consider the problem of computing market equilibria and show three results. (i) For exchange economies satisfying weak gross substitutability we analyze a simple discrete versi...
169
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EWSN
2007
Springer
16 years 6 months ago
2007
Springer
Methods for node localisation in sensor networks usually rely upon the measurement of received strength, time-of-arrival, and/or angle-of-arrival of an incoming signal. In this pap...
162
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ICCAD
2004
IEEE
16 years 3 months ago
2004
IEEE
Closed formed expressions for buffered interconnect delay approximation have been around for some time. However, previous approaches assume that buffers are free to be placed anyw...