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» Timing model reduction for hierarchical timing analysis
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ITC
1997
IEEE
73views Hardware» more  ITC 1997»
15 years 10 months ago
A Low-Overhead Design for Testability and Test Generation Technique for Core-Based Systems
In a fundamental paradigm shift in system design, entire systems are being built on a single chip, using multiple embedded cores. Though the newest system design methodology has s...
Indradeep Ghosh, Niraj K. Jha, Sujit Dey
LCTRTS
2009
Springer
16 years 1 months ago
A compiler optimization to reduce soft errors in register files
Register file (RF) is extremely vulnerable to soft errors, and traditional redundancy based schemes to protect the RF are prohibitive not only because RF is often in the timing c...
Jongeun Lee, Aviral Shrivastava
PLDI
1990
ACM
15 years 10 months ago
A Fresh Look at Optimizing Array Bound Checking
- This paper describes techniques for optimizing range checks performed to detect array bound violations. In addition to the elimination of range check:s, the optimizations discuss...
Rajiv Gupta
DIAL
2004
IEEE
170views Image Analysis» more  DIAL 2004»
15 years 10 months ago
A General System for the Retrieval of Document Images from Digital Libraries
Large collections of scanned documents (books and journals) are now available in Digital Libraries. The most common method for retrieving relevant information from these collectio...
Simone Marinai, Emanuele Marino, Francesca Cesarin...
ECOOP
2012
Springer
13 years 9 months ago
Static Detection of Loop-Invariant Data Structures
As a culture, object-orientation encourages programmers to create objects, both short- and long-lived, without concern for cost. Excessive object creation and initialization can ca...
Guoqing (Harry) Xu, Dacong Yan, Atanas Rountev