4164 search results - page 453 / 833 » Timing model reduction for hierarchical timing analysis |
191
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ICPP
2008
IEEE
16 years 1 months ago
2008
IEEE
In this paper we consider gossip-based Peer-to-Peer streaming applications where multiple sources exist and they work serially. More specifically, we tackle the problem of fast s...
168
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ISCAS
2008
IEEE
16 years 1 months ago
2008
IEEE
—In this paper, an energy-efficient and high performance ternary content addressable memory (TCAM) are presented. It employs the concept of “green” microarchitecture and circ...
160
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COLT
2007
Springer
16 years 1 months ago
2007
Springer
Abstract. We consider the problem of learning an acyclic discrete circuit with n wires, fan-in bounded by k and alphabet size s using value injection queries. For the class of tran...
186
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FPL
2007
Springer
16 years 1 months ago
2007
Springer
This paper presents a novel architecture for domain-specific FPGA devices. This architecture can be optimised for both speed and density by exploiting domain-specific informatio...
194
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MICRO
2006
IEEE
16 years 26 days ago
2006
IEEE
The superblock is a scheduling region which exposes instruction level parallelism beyond the basic block through speculative execution of instructions. In general, scheduling supe...