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» Timing model reduction for hierarchical timing analysis
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HASE
2007
IEEE
16 years 1 months ago
Simulation Models and Implementation of a Simulator for the Performability Analysis of Electric Power Systems Considering Interd
Electric Power Systems (EPS) become more and more critical for our society, since they provide vital services for the human activities. At the same time, obtaining dependable beha...
Francesco Romani, Silvano Chiaradonna, Felicita Di...
ISQED
2009
IEEE
187views Hardware» more  ISQED 2009»
16 years 1 months ago
An efficient current-based logic cell model for crosstalk delay analysis
 Electrical Modeling for High Bandwidth IO Link  Chirayu Amin, Chandramouli Kashyap ¬ Intel Corp., Hillsboro, OR  Prateek Bhansali ¬ Univ. of Minnesota, Mi...
Debasish Das, William Scott, Shahin Nazarian, Hai ...
DATE
2003
IEEE
122views Hardware» more  DATE 2003»
16 years 1 days ago
A General Framework for Analysing System Properties in Platform-Based Embedded System Designs
We present a framework (Real-Time Calculus) for analysing various system properties pertaining to timing analysis, loads on various components and on-chip buffer memory requiremen...
Samarjit Chakraborty, Simon Künzli, Lothar Th...
BMCBI
2011
15 years 1 months ago
N-gram analysis of 970 microbial organisms reveals presence of biological language models
Background: It has been suggested previously that genome and proteome sequences show characteristics typical of natural-language texts such as “signature-style” word usage ind...
Hatice U. Osmanbeyoglu, Madhavi Ganapathiraju
ALGORITHMICA
2010
153views more  ALGORITHMICA 2010»
15 years 6 months ago
Confluently Persistent Tries for Efficient Version Control
We consider a data-structural problem motivated by version control of a hierarchical directory structure in a system like Subversion. The model is that directories and files can b...
Erik D. Demaine, Stefan Langerman, Eric Price