4164 search results - page 285 / 833 » Timing model reduction for hierarchical timing analysis |
164
Voted
WSC
1997
15 years 8 months ago
1997
Excellent production design and planning depends on accurate simulation of a high quality layout. A good layout project will always begin with an analysis of the production volume...
183
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GLVLSI
2009
IEEE
15 years 10 months ago
2009
IEEE
A methodology is proposed to efficiently estimate the substrate noise generated by large scale aggressor circuits. Small spatial voltage differences within the ground distribution...
191
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TCAD
2002
15 years 6 months ago
2002
This paper introduces an accurate analysis of on-chip inductance effects for distributed interconnects that takes the effect of both the series resistance and the output parasitic ...
193
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NJC
2006
15 years 6 months ago
2006
Abstract. We present a new parallel computation model called the Parallel ResourceOptimal computation model. PRO is a framework being proposed to enable the design of efficient and...
168
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MASCOTS
2007
15 years 8 months ago
2007
Network performance analysis relies mainly on two models: a workload model and a performance model. This paper proposes to use histograms for characterising the arrival workloads ...