4164 search results - page 260 / 833 » Timing model reduction for hierarchical timing analysis |
173
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ICCAD
2006
IEEE
16 years 3 months ago
2006
IEEE
Meeting timing constraint is one of the most important issues for modern design automation tools. This situation is exacerbated with the existence of process variation. Current hi...
144
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DATE
2003
IEEE
15 years 12 months ago
2003
IEEE
We propose a technique for compressing test vectors. The technique reduces test application time and tester memory requirements by utilizing part of the predecessor response in co...
181
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ERSA
2006
15 years 8 months ago
2006
In this case study, various ways to partition a code between the microprocessor and FPGA are examined. Discrete image convolution operation with separable kernel is used as the ca...
179
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GRID
2006
Springer
15 years 6 months ago
2006
Springer
In this paper we propose a systematic approach to performance analysis of workflow applications on the Grid. We introduce an ideal model for the workflow execution time and explain...
178
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GLVLSI
2005
IEEE
16 years 7 days ago
2005
IEEE
A hierarchical scheme with cells and modules is crucial for managing design complexity during a large integrated circuit design. We present a methodology for thermal aware cell-ba...