4164 search results - page 236 / 833 » Timing model reduction for hierarchical timing analysis |
166
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ISCAS
1999
IEEE
15 years 11 months ago
1999
IEEE
A method for modeling complex CMOS gates by the reduction of each gate to an effective equivalent inverter is introduced. The conducting and parasitic behavior of parallel and ser...
158
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DATE
2004
IEEE
15 years 10 months ago
2004
IEEE
The analysis of real-time properties of an embedded system usually relies on the worst-case execution times (WCET) of the tasks to be executed. In contrast to that, in real world ...
175
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DDECS
2009
IEEE
15 years 10 months ago
2009
IEEE
Although the Neighborhood Pattern Sensitive Fault (NPSF) model is recognized as a high quality fault model for memory arrays, the excessive test application time cost associated wi...
185
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SRDS
2003
IEEE
15 years 12 months ago
2003
IEEE
Many mathematical models have been proposed to evaluate the execution performance of an application with and without checkpointing in the presence of failures. They assume that th...
153
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GPCE
2007
Springer
16 years 23 days ago
2007
Springer
Every notion of a component for the development of embedded systems has to take heterogeneity into account: components may be hardware or software or OS, synchronous or asynchrono...