4164 search results - page 235 / 833 » Timing model reduction for hierarchical timing analysis |
207
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MICRO
1999
IEEE
15 years 11 months ago
1999
IEEE
Current microprocessors incorporate techniques to exploit instruction-level parallelism (ILP). However, previous work has shown that these ILP techniques are less effective in rem...
183
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GECCO
2004
Springer
15 years 12 months ago
2004
Springer
Abstract. The need for supporting CSCW applications with heterogeneous and varying user requirements calls for adaptive and reconfigurable schedulers accommodating a mixture of re...
162
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WSC
2007
15 years 9 months ago
2007
Fluctuations of work-in-progress (WIP) levels cause variability of cycle time and often lead to productivity losses in semiconductor wafer fabrication plants. To identify sources ...
167
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CAV
2003
Springer
15 years 11 months ago
2003
Springer
In previous work, we showed how structural information can be used to efficiently generate the state-space of asynchronous systems. Here, we apply these ideas to symbolic CTL model...
181
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ICC
2007
IEEE
16 years 28 days ago
2007
IEEE
— In sensor networks, MAC protocols based on Time Division Multiple Access (TDMA) with wakeup and sleep periods have attracted considerable interest because of their low power co...