4164 search results - page 209 / 833 » Timing model reduction for hierarchical timing analysis |
167
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WSCG
2001
15 years 8 months ago
2001
In computer graphics and engineering many classes of complex objects can be designed with L-systems. We present a concept for enhancing timed and parametric L-systems with physics...
162
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ICCAD
2006
IEEE
16 years 3 months ago
2006
IEEE
Abstract— Chip-package thermal analysis is necessary for the design and synthesis of reliable, high-performance, low-power, compact integrated circuits (ICs). Many methods of IC ...
201
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CODES
2002
IEEE
15 years 11 months ago
2002
IEEE
In this paper we present a method to perform static timing analysis of SystemC models, that describe parallel, communicating software processes.The paper combines a worstcase exec...
153
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IPPS
2005
IEEE
16 years 4 days ago
2005
IEEE
— Schedule synthesis based on reachability analysis of timed automata has received attention in the last few years. The main strength of this approach is that the expressiveness ...
170
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FPL
2008
Springer
15 years 8 months ago
2008
Springer
This paper considers the implementation of an annealing technique for dynamic power reduction in FPGAs. The proposed method comprises a power-aware objective function for placemen...