4164 search results - page 177 / 833 » Timing model reduction for hierarchical timing analysis |
181
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TCAD
2008
15 years 6 months ago
2008
Physical synthesis tools are responsible for achieving timing closure. Starting with 130nm designs, multiple cycles are required to cross the chip, making latch placement critical...
172
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GPC
2007
Springer
16 years 20 days ago
2007
Springer
This paper focuses on two problems related to QoS-aware I/O server placement in hierarchical Grid environments. Given a hierarchical network with requests from clients, the network...
175
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DAC
2005
ACM
15 years 8 months ago
2005
ACM
Minimizing power consumption is one of the most important objectives in IC design. Resizing gates and assigning different Vt’s are common ways to meet power and timing budgets. ...
164
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ESANN
2008
15 years 8 months ago
2008
This work advances the Support Vector Machine (SVM) based approach for predictive modelling of failure time data as proposed in [1]. The main results concern a drastic reduction in...
173
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ICRA
2007
IEEE
16 years 24 days ago
2007
IEEE
— This paper extends the notion of residuals for fault detection, well known in the continuous system to the timed discrete events systems. The aim is to design the fault indicat...