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» Timing model reduction for hierarchical timing analysis
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HPCA
2005
IEEE
16 years 6 months ago
Voltage and Frequency Control With Adaptive Reaction Time in Multiple-Clock-Domain Processors
Dynamic voltage and frequency scaling (DVFS) is a widely-used method for energy-efficient computing. In this paper, we present a new intra-task online DVFS scheme for multiple clo...
Qiang Wu, Philo Juang, Margaret Martonosi, Douglas...
ICPR
2002
IEEE
16 years 7 months ago
Hierarchical Recognition of Intentional Human Gestures for Sports Video Annotation
We present a novel technique for the recognition of complex human gestures for video annotation using accelerometers and the hidden Markov model. Our extension to the standard hid...
Graeme S. Chambers, Svetha Venkatesh, Geoff A. W. ...
ISQED
2003
IEEE
133views Hardware» more  ISQED 2003»
15 years 11 months ago
Impact of Interconnect Pattern Density Information on a 90nm Technology ASIC Design Flow
The importance of an interconnect pattern density model in ASIC design flow for a 90nm technology is presented. It is shown that performing the timing analysis at the worst-case c...
Payman Zarkesh-Ha, S. Lakshminarayann, Ken Doniger...
IFM
2007
Springer
245views Formal Methods» more  IFM 2007»
16 years 19 days ago
Co-simulation of Distributed Embedded Real-Time Control Systems
Development of computerized embedded control systems is difficult because it brings together systems theory, electrical engineering and computer science. The engineering and analys...
Marcel Verhoef, Peter Visser, Jozef Hooman, Jan F....
ICSE
2001
IEEE-ACM
15 years 11 months ago
Designing Concurrent, Distributed, and Real-Time Applications with UML
Object-oriented concepts are crucial in software design because they address fundamental issues of adaptation and evolution. With the proliferation of object-oriented notations an...
Hassan Gomaa