4164 search results - page 144 / 833 » Timing model reduction for hierarchical timing analysis |
162
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ICCAD
2005
IEEE
16 years 3 months ago
2005
IEEE
— Variability in the chip design process has been relatively increasing with technology scaling to smaller dimensions. Using worst case analysis for circuit optimization severely...
158
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RTSS
2005
IEEE
15 years 12 months ago
2005
IEEE
This paper focuses on the hierarchical scheduling of systems where a number of separate applications reside on a single processor. It addresses the particular case where fixed pri...
165
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ICPR
2008
IEEE
16 years 25 days ago
2008
IEEE
This paper presents a new algorithm named Kernel Bisecting k-means and Sample Removal (KBK-SR) as a sampling preprocessing for SVM training to improve the scalability. The novel c...
174
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GLVLSI
2010
IEEE
15 years 8 months ago
2010
IEEE
For timing-driven or yield-driven designs, non-tree routing has become more and more popular and additional loops provide the redundant paths to protect against the effect of the ...
163
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APN
2003
Springer
15 years 11 months ago
2003
Springer
Model checking by exhaustive state space enumeration is one of the most developed analysis methods for distributed event systems. Its main problem—the size of the state spaces—...