Sciweavers

4164 search results - page 130 / 833
» Timing model reduction for hierarchical timing analysis
Sort
View
ICCD
2004
IEEE
106views Hardware» more  ICCD 2004»
16 years 3 months ago
Gate Sizing and V{t} Assignment for Active-Mode Leakage Power Reduction
Leakage current is a key factor in IC power consumption even in the active operating mode. We investigate the simultaneous optimization of gate size and threshold voltage to reduc...
Feng Gao, John P. Hayes
IJAR
2008
95views more  IJAR 2008»
15 years 6 months ago
Rule reduction for efficient inferencing in similarity based reasoning
The two most important models of inferencing in approximate reasoning with fuzzy sets are Zadeh's Compositional Rule of Inference (CRI) and Similarity Based Reasoning (SBR). ...
Balasubramaniam Jayaram
BMCBI
2007
176views more  BMCBI 2007»
15 years 6 months ago
Genome Expression Pathway Analysis Tool - Analysis and visualization of microarray gene expression data under genomic, proteomic
Background: Regulation of gene expression is relevant to many areas of biology and medicine, in the study of treatments, diseases, and developmental stages. Microarrays can be use...
Markus Weniger, Julia C. Engelmann, Jörg Schu...
CORR
2010
Springer
58views Education» more  CORR 2010»
15 years 6 months ago
Timed Automata Semantics for Analyzing Creol
ir end-to-end deadlines. Real-time Creol can be useful for analyzing, for instance, abstract models of multi-core embedded systems. We show how analysis can be done in UPPAAL.
Mohammad Mahdi Jaghoori, Tom Chothia
VLSID
2003
IEEE
180views VLSI» more  VLSID 2003»
16 years 6 months ago
Automating Formal Modular Verification of Asynchronous Real-Time Embedded Systems
Most verification tools and methodologies such as model checking, equivalence checking, hardware verification, software verification, and hardware-software coverification often fl...
Pao-Ann Hsiung, Shu-Yu Cheng