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» Timing model reduction for hierarchical timing analysis
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ISPD
1997
ACM
104views Hardware» more  ISPD 1997»
15 years 10 months ago
Timing driven placement in interaction with netlist transformations
In this paper, we present a new approach that performs timing driven placement for standard cell circuits in interaction with netlist transformations. As netlist transformations a...
Guenter Stenz, Bernhard M. Riess, Bernhard Rohflei...
GECCO
2005
Springer
160views Optimization» more  GECCO 2005»
15 years 12 months ago
On the complexity of hierarchical problem solving
Competent Genetic Algorithms can efficiently address problems in which the linkage between variables is limited to a small order k. Problems with higher order dependencies can onl...
Edwin D. de Jong, Richard A. Watson, Dirk Thierens
PADS
2004
ACM
15 years 11 months ago
Event Reconstruction in Time Warp
In optimistic simulations, checkpointing techniques are often used to reduce the overhead caused by state saving. In this paper, we propose event reconstruction as a technique wit...
Lijun Li, Carl Tropper
ISPD
2003
ACM
110views Hardware» more  ISPD 2003»
15 years 11 months ago
Explicit gate delay model for timing evaluation
Delay evaluation is always a crucial concern in the VLSI design and it becomes increasingly more critical in the nowadays deep-submicron technology. To obtain an accurate delay va...
Muzhou Shao, Martin D. F. Wong, Huijing Cao, Youxi...
AINA
2008
IEEE
16 years 25 days ago
Missing Value Estimation for Time Series Microarray Data Using Linear Dynamical Systems Modeling
The analysis of gene expression time series obtained from microarray experiments can be effectively exploited to understand a wide range of biological phenomena from the homeostat...
Connie Phong, Raul Singh