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» Timing model reduction for hierarchical timing analysis
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ASPDAC
2008
ACM
169views Hardware» more  ASPDAC 2008»
15 years 8 months ago
Analytical model for the impact of multiple input switching noise on timing
The timing models used in current Static Timing Analysis tools use gate delays only for single input switching events. It is well known that the temporal proximity of signals arriv...
Rajeshwary Tayade, Sani R. Nassif, Jacob A. Abraha...
TPDS
2008
76views more  TPDS 2008»
15 years 6 months ago
How to Choose a Timing Model
When employing a consensus algorithm for state machine replication, should one optimize for the case that all communication links are usually timely, or for fewer timely links? Do...
Idit Keidar, Alexander Shraer
CMSB
2007
Springer
16 years 15 days ago
Context Sensitivity in Logical Modeling with Time Delays
For modeling and analyzing regulatory networks based on qualitative information and possibly additional temporal constraints, approaches using hybrid automata can be very helpful. ...
Heike Siebert, Alexander Bockmayr
CVPR
2012
IEEE
13 years 8 months ago
Sasaki metrics for analysis of longitudinal data on manifolds
Longitudinal data arises in many applications in which the goal is to understand changes in individual entities over time. In this paper, we present a method for analyzing longitu...
Prasanna Muralidharan, P. Thomas Fletcher
RTS
2008
131views more  RTS 2008»
15 years 5 months ago
Formal verification of multitasking applications based on timed automata model
The aim of this paper is to show, how a multitasking application running under a real-time operating system compliant with an OSEK/VDX standard can be modeled by timed automata. Th...
Libor Waszniowski, Zdenek Hanzálek