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» Timing driven power gating
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ISCAS
2002
IEEE
141views Hardware» more  ISCAS 2002»
15 years 10 months ago
Power characterization of digital filters implemented on FPGA
The evaluation of power consumption in complex digital systems is a hard task that normally requires long simulation time and complicated models. In this work, we obtain power con...
Gian-Carlo Cardarilli, Andrea Del Re, Alberto Nann...
ASPDAC
2007
ACM
99views Hardware» more  ASPDAC 2007»
15 years 9 months ago
Shelf Packing to the Design and Optimization of A Power-Aware Multi-Frequency Wrapper Architecture for Modular IP Cores
Abstract-- This paper proposes a novel power-aware multifrequency wrapper architecture design to achieve at-speed testability. The trade-offs between power dissipation, scan time a...
Dan Zhao, Unni Chandran, Hideo Fujiwara
ICCAD
1995
IEEE
106views Hardware» more  ICCAD 1995»
15 years 9 months ago
Re-engineering of timing constrained placements for regular architectures
In a typical design ow, the design may be altered slightly several times after the initial design cycle according to minor changes in the design speci cation either as a result o...
Anmol Mathur, K. C. Chen, C. L. Liu
IJCNN
2006
IEEE
15 years 12 months ago
Real-Time Implementation of an Optimal Transient Neurocontroller for a GCSC
—This paper presents the design of an optimal Auxiliary Transient Neurocontroller (ATNC) for the Gate Controlled Series Capacitor (GCSC) in a multi-machine power system. GCSC is ...
Swakshar Ray, Ganesh K. Venayagamoorthy
RSP
2005
IEEE
164views Control Systems» more  RSP 2005»
15 years 11 months ago
High Level Synthesis for Data-Driven Applications
Abstract— John von Neumann proposed his famous architecture in a context where hardware was very expensive and bulky. His goal was to maximize functionality with minimal hardware...
Etienne Bergeron, Xavier Saint-Mleux, Marc Feeley,...