395 search results - page 35 / 79 » Timed circuits: a new paradigm for high-speed design |
169
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GLVLSI
2000
IEEE
15 years 10 months ago
2000
IEEE
Circuit interconnect has become a substantial obstacle in the design of high performance systems. In this paper we explore a new routing paradigm that strikes at the root of the i...
123
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ISLPED
2005
ACM
15 years 11 months ago
2005
ACM
Reducing power dissipation and testing time is accomplished by forming two clusters of don’t-care bit inside an input and a response test cube. New reordering scheme of scan lat...
145
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ICCAD
2001
IEEE
16 years 3 months ago
2001
IEEE
Retiming is a widely investigated technique for performance optimization. It performs powerful modifications on a circuit netlist. However, often it is not clear, whether the pred...
156
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ETS
2011
IEEE
14 years 5 months ago
2011
IEEE
—In-field diagnosability of electronic components in larger systems such as automobiles becomes a necessity for both customers and system integrators. Traditionally, functional ...
191
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DATE
2002
IEEE
15 years 11 months ago
2002
IEEE
In this paper we propose a new compression algorithm geared to reduce the time needed to test scan-based designs. Our scheme compresses the test vector set by encoding the bits th...