395 search results - page 11 / 79 » Timed circuits: a new paradigm for high-speed design |
195
Voted
GLVLSI
2007
IEEE
16 years 12 days ago
2007
IEEE
We present new timing and congestion driven FPGA placement algorithms with minimal runtime overhead. By predicting the post-routing critical edges and estimating congestion accura...
184
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ICCAD
1995
IEEE
15 years 9 months ago
1995
IEEE
In this paper we investigate activity-driven clock trees to reduce the dynamic power consumption of synchronous digital CMOS circuits. Sections of an activity-driven clock tree ca...
126
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GLVLSI
2003
IEEE
15 years 11 months ago
2003
IEEE
In this paper, we describe a low power and high speed multiplier suitable for standard cell-based ASIC design methodologies. For the purpose, an optimized booth encoder, compact 2...
153
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ICCAD
1995
IEEE
15 years 9 months ago
1995
IEEE
In a typical design
ow, the design may be altered slightly several times after the initial design cycle according to minor changes in the design speci cation either as a result o...
145
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DATE
2009
IEEE
16 years 25 days ago
2009
IEEE
Soft errors in combinational and sequential elements of digital circuits are an increasing concern as a result of technology scaling. Several techniques for gate and latch hardeni...