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ICCD
2006
IEEE
103views Hardware» more  ICCD 2006»
16 years 4 months ago
Requirements and Concepts for Transaction Level Assertions
— The latest development of hardware design and ation methodologies shows a trend towards abstraction levels higher than RTL, referred to as transaction level (TL). Transaction l...
Wolfgang Ecker, Volkan Esen, Michael Hull, Thomas ...
ICCD
2005
IEEE
119views Hardware» more  ICCD 2005»
16 years 4 months ago
Deployment of Better Than Worst-Case Design: Solutions and Needs
The advent of nanometer feature sizes in silicon fabrication has triggered a number of new design challenges for computer designers. These challenges include design complexity and...
Todd M. Austin, Valeria Bertacco
ICCD
2005
IEEE
246views Hardware» more  ICCD 2005»
16 years 4 months ago
H-SIMD Machine: Configurable Parallel Computing for Matrix Multiplication
FPGAs (Field-Programmable Gate Arrays) are often used as coprocessors to boost the performance of dataintensive applications [1, 2]. However, mapping algorithms onto multimillion-...
Xizhen Xu, Sotirios G. Ziavras
ICCD
2004
IEEE
87views Hardware» more  ICCD 2004»
16 years 4 months ago
Fetch Halting on Critical Load Misses
As the performance gap between processors and memory systems increases, the CPU spends more time stalled waiting for data from main memory. Critical long latency instructions, suc...
Nikil Mehta, Brian Singer, R. Iris Bahar, Michael ...
ICCD
2004
IEEE
111views Hardware» more  ICCD 2004»
16 years 4 months ago
Power-Aware Deterministic Block Allocation for Low-Power Way-Selective Cache Structure
This paper proposes a power-aware cache block allocation algorithm for the way-selective setassociative cache on embedded systems to reduce energy consumption without additional d...
Jung-Wook Park, Gi-Ho Park, Sung-Bae Park, Shin-Du...
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