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VALUETOOLS
2006
ACM
167views Hardware» more  VALUETOOLS 2006»
16 years 1 months ago
Detailed cache simulation for detecting bottleneck, miss reason and optimization potentialities
Cache locality optimization is an efficient way for reducing the idle time of modern processors in waiting for needed data. This kind of optimization can be achieved either on the...
Jie Tao, Wolfgang Karl
CODES
2005
IEEE
16 years 1 months ago
DVS for buffer-constrained architectures with predictable QoS-energy tradeoffs
We present a new scheme for dynamic voltage and frequency scaling (DVS) for processing multimedia streams on architectures with restricted buffer sizes. The main advantage of our ...
Alexander Maxiaguine, Samarjit Chakraborty, Lothar...
DATE
2005
IEEE
136views Hardware» more  DATE 2005»
16 years 1 months ago
Increasing Register File Immunity to Transient Errors
Transient errors are one of the major reasons for system downtime in many systems. While prior research has mainly focused on the impact of transient errors on datapath, caches an...
Gokhan Memik, Mahmut T. Kandemir, Ozcan Ozturk
GLVLSI
2005
IEEE
124views VLSI» more  GLVLSI 2005»
16 years 1 months ago
A first look at the interplay of code reordering and configurable caches
The instruction cache is a popular target for optimizations of microprocessor-based systems because of the cache’s high impact on system performance and power, and because of th...
Ann Gordon-Ross, Frank Vahid, Nikil Dutt
ICEIS
2005
IEEE
16 years 1 months ago
Conditions for Interoperability
Abstract: Interoperability for information systems remains a challenge both at the semantic and organisational levels. The original three-level architecture for local databases nee...
B. Nick Rossiter, Michael A. Heather
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