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ICCAD
2005
IEEE
176views Hardware» more  ICCAD 2005»
16 years 3 months ago
Statistical gate sizing for timing yield optimization
— Variability in the chip design process has been relatively increasing with technology scaling to smaller dimensions. Using worst case analysis for circuit optimization severely...
Debjit Sinha, Narendra V. Shenoy, Hai Zhou
ASPDAC
2006
ACM
137views Hardware» more  ASPDAC 2006»
16 years 22 days ago
Parameterized block-based non-gaussian statistical gate timing analysis
As technology scales down, timing verification of digital integrated circuits becomes an increasingly challenging task due to the gate and wire variability. Therefore, statistical...
Soroush Abbaspour, Hanif Fatemi, Massoud Pedram
DATE
2003
IEEE
116views Hardware» more  DATE 2003»
16 years 2 days ago
Statistical Timing Analysis Using Bounds
The growing impact of within-die process variation has created the need for statistical timing analysis, where gate delays are modeled as random variables. Statistical timing anal...
Aseem Agarwal, David Blaauw, Vladimir Zolotov, Sar...
IDA
2003
Springer
15 years 12 months ago
Fuzzy Clustering of Short Time-Series and Unevenly Distributed Sampling Points
This paper proposes a new clustering algorithm in the fuzzy-c-means family, which is designed to cluster time series and is particularly suited for short time series and those wit...
Carla S. Möller-Levet, Frank Klawonn, Kwang-H...
CAV
1994
Springer
113views Hardware» more  CAV 1994»
15 years 11 months ago
A Determinizable Class of Timed Automata
We introduce event-recording automata. An event-recording automaton is a timed automaton that contains, for every event a, a clock that records the time of the last occurrence of a...
Rajeev Alur, Limor Fix, Thomas A. Henzinger