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ICCD
2001
IEEE
90views Hardware» more  ICCD 2001»
16 years 3 months ago
Interconnect-centric Array Architectures for Minimum SRAM Access Time
‡ Physical and generic models that analytically couple the array architecture of CMOS SRAMs with the wire lengths and fan-outs along critical paths to decode and sense data are r...
Azeez J. Bhavnagarwala, Stephen V. Kosonocky, Jame...
ISORC
2008
IEEE
16 years 27 days ago
Memory Management for Real-Time Java: State of the Art
The Real-time Specification for Java extends the Java platform to support real-time processing and introduces a region-based memory model, called scoped memory, which side-steps ...
Filip Pizlo, Jan Vitek
RTCSA
2006
IEEE
16 years 16 days ago
Jitter Evaluation of Real-Time Control Systems
The real-time implementation of a controller typically introduces artefacts like delay and jitters that have not been considered at the design stage. As a consequence, the system ...
Manuel Lluesma, Anton Cervin, Patricia Balbastre, ...
ECRTS
2002
IEEE
15 years 11 months ago
Managing Multi-Mode Tasks with Time Cost and Quality Levels using Optimal Discrete Control Synthesis
Real-time control systems are complex to design, and automation support is important. We are interested in systems with multiple tasks, each with multiple modes, implementing a fu...
Hervé Marchand, Éric Rutten
ICCAD
2000
IEEE
91views Hardware» more  ICCAD 2000»
15 years 11 months ago
A Timing-Constrained Algorithm for Simultaneous Global Routing of Multiple Nets
In this paper, we propose a new approach for VLSI interconnect global routing that can optimize both congestion and delay, which are often competing objectives. Our approach provi...
Jiang Hu, Sachin S. Sapatnekar