821 search results - page 99 / 165 » Time Dependent Processing in a Parallel Pipeline Architectur... |
164
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ICCAD
2008
IEEE
16 years 3 months ago
2008
IEEE
— As Double Patterning Technology (DPT) becomes the only solution for 32-nm lithography process, we need to investigate how DPT affects the performance of a chip. In this paper, ...
186
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WSC
1998
15 years 7 months ago
1998
We have taken a NIST molecular dynamics simulation program (md3), which was configured as a single sequential process running on a CRAY C90 vector supercomputer, and parallelized ...
144
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FPL
2003
Springer
15 years 11 months ago
2003
Springer
In this paper we present a single-chip FPGA full encryptor/decryptor core design of the AES algorithm. Our design performs all of them, encryption, decryption and key scheduling pr...
166
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HPCA
2009
IEEE
16 years 6 months ago
2009
IEEE
This paper presents elastic buffers (EBs), an efficient flow-control scheme that uses the storage already present in pipelined channels in place of explicit input virtualchannel b...
160
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ATAL
2007
Springer
16 years 14 days ago
2007
Springer
In this paper we consider the problem of managing and exploiting schedules in an uncertain and distributed environment. We assume a team of collaborative agents, each responsible ...