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ISCA
2007
IEEE
130views Hardware» more  ISCA 2007»
15 years 6 months ago
Non-Inclusion Property in Multi-Level Caches Revisited
The center of gravity of computer architecture is moving toward memory systems. Barring breakthrough microarchitectural techniques to move processor performance to higher levels, ...
Mohamed M. Zahran, Kursad Albayraktaroglu, Manoj F...
SIGMETRICS
2000
ACM
145views Hardware» more  SIGMETRICS 2000»
15 years 6 months ago
The incremental deployability of RTT-based congestion avoidance for high speed TCP Internet connections
Our research focuses on end-to-end congestion avoidance algorithms that use round trip time (RTT) fluctuations as an indicator of the level of network congestion. The algorithms a...
Jim Martin, Arne A. Nilsson, Injong Rhee
DSD
2010
IEEE
112views Hardware» more  DSD 2010»
15 years 5 months ago
Re-NUCA: Boosting CMP Performance Through Block Replication
— Chip Multiprocessor (CMP) systems have become the reference architecture for designing micro-processors, thanks to the improvements in semiconductor nanotechnology that have co...
Pierfrancesco Foglia, Cosimo Antonio Prete, Marco ...
SAT
2010
Springer
165views Hardware» more  SAT 2010»
15 years 5 months ago
An Empirical Study of Optimal Noise and Runtime Distributions in Local Search
This paper presents a detailed empirical study of local search for Boolean satisfiability (SAT), highlighting several interesting properties, some of which were previously unknown...
Lukas Kroc, Ashish Sabharwal, Bart Selman
ACSD
2010
IEEE
251views Hardware» more  ACSD 2010»
15 years 4 months ago
Modular Interpretation of Heterogeneous Modeling Diagrams into Synchronous Equations Using Static Single Assignment
Abstract--The ANR project SPaCIFY develops a domainspecific programming environment, Synoptic, to engineer embedded software for space applications. Synoptic is an Eclipse-based mo...
Jean-Pierre Talpin, Julien Ouy, Thierry Gautier, L...