6111 search results - page 981 / 1223 » Time, Hardware, and Uniformity |
217
click to vote
DAC
2011
ACM
14 years 6 months ago
2011
ACM
As transistor dimensions continue to scale deep into the nanometer regime, silicon reliability is becoming a chief concern. At the same time, transistor counts are scaling up, ena...
255
click to vote
ISPD
2012
ACM
14 years 2 months ago
2012
ACM
Gate sizing in VLSI design is a widely-used method for power or area recovery subject to timing constraints. Several previous works have proposed gate sizing heuristics for power ...
209
click to vote
ISCA
2012
IEEE
13 years 9 months ago
2012
IEEE
When multiple processor (CPU) cores and a GPU integrated together on the same chip share the off-chip main memory, requests from the GPU can heavily interfere with requests from t...
174
click to vote
ICCAD
2003
IEEE
15 years 12 months ago
2003
IEEE
This paper presents several important enhancements to the recently published multilevel placement package mPL [12]. The improvements include (i) unconstrained quadratic relaxation...
200
click to vote
ICALP
2009
Springer
16 years 7 months ago
2009
Springer
We present an AC1 (logDCFL) algorithm for checking LTL formulas over finite paths, thus establishing that the problem can be efficiently parallelized. Our construction provides a f...